The present invention relates generally to circuit verification and more specifically to generation of test programs useful in circuit verification or validation.
Validation may be one of the most challenging tasks in processor design. Processor validation is often accomplished, at least in part, by executing programs on the processor, or on intermediate models of the processor, and comparing results of the programs against a model.
The ability to find errors in the processor is often dependent on the quality of the test programs. Designers often prepare some test programs manually to target a specific portion of the processor. For the rest of the processor, designers often use randomly generated test programs or real application programs to validate the entire processor.
A designer's insights and experience sometimes result in the manually generated test programs being useful in finding design errors in a specific part of the processor. On the other hand, writing test programs manually may be time consuming and generally cannot be used to generate long programs to validate an entire processor design. Another problem with manual generation is that the designer writing the programs should have a good understanding of the design, and the number of such people is generally limited.
Long randomly generated test programs or application programs can be used to validate the entire processor, but such programs may not target a specific portion of the processor and validate that portion under different scenarios.
As a third approach, it is possible to use an automatic tool to generate test programs based on the actual implementation of the processor. This approach helps to generate test programs to validate some implementation details that can be missed by other methods.